Merge Sort Core

Merge Sort Core is customizable and can be tailored to customer needs.


  • Optimized design allows customers to target cost efficient FPGAs.
  • Can be tailored to customer needs
  • Fully synchronous design using only one clock
  • Area/Power efficient architecture
  • Netlist or synthesizable RTL source code in VHDL
  • Comprehensive verification test bench and vectors in VHDL
  • Integration documentation and user guide

This decoder is written in VHDL, capable of being used on any FPGA/ASIC architecture.