Products
Netlist or synthesizable RTL source code in VHDL, Comprehensive verification test bench and vectors in VHDL, Integration documentation and user guide.
- Consists of Conjugation unit, Complex Multiplier, Pre-adder and two Complex Accumulators (X and Y).
- Parameterizable input widths
- Parameterizable accumulator widths
- Full precision multiplier output available
- Integer and fractional fixed point arithmetic capability
- Supports operations such as Multiply, Multiply and Accumulate (Add/Subtract), Load Accumulator with external accumulator inputs, Multiply and Add/Subtract to external accumulator input and Multiply and Add/Subtract to external pre-add inputs.
- Supports common configurations such as MAC for Filters, FFT Butterfly, Correlation/Matched Filter and Sliding Window Correlator and many more.
- Fully synchronous design using only one clock
- User friendly control interface
- Silicon verified in multiple devices
Reed-Solomon Decoder Core is Parameterisable and can also decode shortened and punctured codes.
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Parameterisable primitive polynomial.
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Parameterisable symbol size (code block length)
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Parameterisable number of correctable errors
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Parameterisable input buffer size
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Decodes shortened and punctured codes
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Fully synchronous using single clock
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User friendly interface.
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Area efficient design
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Silicon verified in multiple devices
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Optimized for WMAN (802.16), DVB and other OFDM standards
Viterbi Decoder Core is parameterisable and is optimized for WLAN (802.11a/g, 802.16), DVB and other OFDM standards.
This core is optimized for high-speed operation.
- Hard or soft decoder with configurable soft bit widths
- Parameterisable generator polynomials
- Parameterisable code Constraint length
- Parameterisable trace-back length
- Support erasures (code puncturing)
- Fully synchronous design using only one clock
- 1 decoded bit per clock cycle throughput
- Automatic internal metric rescaling
- Low latency
- Optimized design allowing high-speed operation
- User friendly control interface
- Silicon verified in multiple devices
- Optimized for WLAN (802.11a/g, 802.16), DVB and other OFDM standards
WiMAX Receiver Core is customizable and can be tailored to customer needs.
- Patented OFDM Synchronization Technology.
- Optimized design allows customers to target cost efficient FPGAs.
- Can be tailored to customer needs
- Fully synchronous design using only one clock
- Area/Power efficient architecture
Merge Sort Core is customizable and can be tailored to customer needs.
- Optimized design allows customers to target cost efficient FPGAs.
- Can be tailored to customer needs
- Fully synchronous design using only one clock
- Area/Power efficient architecture
Spectrum Sensing Core is customizable and can be tailored to customer needs.
- Parameterisable input bit width
- Parameterisable FFT size
- Parameterisable HMM window length
- Parameterisable Power Spectrum bity width
- Detects multiple interferers
- Fully synchronous design using only one clock
- Automatic internal re-scalling
- Low latency
- User friendly control interface
- Silicon verified in multiple devices
- Can be tailored to customer needs
- Area/Power efficient architecture
Reciprocal Core is customizable and can be tailored to customer needs.
- Parameterisable input width
- Parameterisable fractional width input
- Very close reciprocal approximate output
- Area/Power efficient architecture
- Can be used in any hardware implementations where typically division may be avoided
- Fully synchronous design using only one clock
- No multipliers are used/required in the design
- Form factor only dependent on input bit width. Area grows at a rate less than linear input bit width.
- Silicon verified in multiple devices
- Optimized design allows customers to target cost efficient FPGAs.
- Can be tailored to customer needs
DVB-GSE encapsulator IP cores for IPv4/IPv6 network-layer traffic, and utilising AXI4-Stream interconnects for receiving IP packets, and for producing BBFRAME output.
- GSE fragmentation & encapsulation of IPv4/IPv6 packets
- Designed for high throughput1 and low latency
- Supports GSE packet header types for no labels, 6 byte labels, label reuse, for label-based filtering
- Parameterisable MTU’s and SRAM/buffer sizes
- Low (logic and SRAM) resource usage
- Support for both 16200b and 64800b BBFRAME’s, and all DATA FIELD sizes
- AXI4-Stream (8-bit) Interconnect
- Wishbone (SPEC B4) interface for control and packet/device statistics
- Includes BBFRAME generator, stream MUX & scheduler, and padding & scrambling cores
- Robust exception handling and with rapid recovery from exceptions (due to overflows & invalid input data)
- FPGA-proven with Xilinx and Microsemi devices
DVB-GSE de-encapsulator IP cores for IPv4/IPv6 network-layer traffic, and utilising a DVB-SPI-like interconnect for recieved BBFRAME’s, and AXI4-Stream interconnect for PDU output.
- GSE de-encapsulation and PDU re-assembly for IPv4/IPv6 packets
- Designed for high throughput and low latency
- Supports GSE packet header types for no labels, 6 byte labels, label reuse, and label-based filtering
- Parameterisable MTU’s and SRAM/buffer sizes
- Low (logic and SRAM) resource usage
- Support for both 16200b and 64800b BBFRAME’s, and all DATA FIELD sizes
- AXI4-Stream (8-bit) Interconnect
- Wishbone (SPEC B4) interface for control and packet/device statistics
- Includes BBFRAME parser, stream de-MUX, and de-scrambling cores
- Robust exception handling and with rapid recovery from
DVB-GSE encapsulator and de-encapsulator IP cores with AXI4-Stream interconnect to/from (RG)MII interfaces.
- GSE encapsulation of Ethernet frames (via the DVB-GSE Bridged Frame Mandatory Extension Header)
- Designed for high throughput and low latency
- Configurable MTU’s, SRAM/buffer sizes, and packing & fragmentation modes
- Supports GSE packet header types for no labels, 6 byte labels, label reuse, and label-based filtering
- Low (logic and SRAM) resource usage
- Support for both 16200b and 64800b BBFRAME’s, and all DATA FIELD sizes
- AXI4-Stream Interconnect (to/from PHY’s and FEC units)
- Wishbone (SPEC B4) interface for control and packet/device statistics
- CRC-8 for BBFRAME’s, and CRC-32 for reassembled PDU’s and Ethernet frames
- Robust exception handling and with rapid recovery from exceptions (due to overflows & invalid input data)
- Can be configured for single- or dual- clock operation