WiMAX Receiver Core
This decoder is written in VHDL, capable of being used on any FPGA/ASIC architecture.
WiMAX Receiver Core is customizable and can be tailored to customer needs.
- Patented OFDM Synchronization Technology.
- Optimized design allows customers to target cost efficient FPGAs.
- Can be tailored to customer needs
- Fully synchronous design using only one clock
- Area/Power efficient architecture
- Netlist or synthesizable RTL source code in VHDL
- Comprehensive verification test bench and vectors in VHDL
- Integration documentation and user guide
Note 1: Clock Rate = 100 MHz
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