Cognitive Radio - Spectrum Sensing Core

Spectrum Sensing Core is customizable and can be tailored to customer needs.

  • Parameterisable input bit width
  • Parameterisable FFT size
  • Parameterisable HMM window length
  • Parameterisable Power Spectrum bity width
  • Detects multiple interferers
  • Fully synchronous design using only one clock
  • Automatic internal re-scalling
  • Low latency
  • User friendly control interface
  • Silicon verified in multiple devices
  • Can be tailored to customer needs
  • Area/Power efficient architecture
  • Netlist or synthesizable RTL source code in VHDL
  • Comprehensive verification test bench and vectors in VHDL
  • Integration documentation and user guide

The spectrum sensing core blindly detects occupied sub-carriers within a wideband spectrum. The algorithm implemented in this core uses a patented algorithm (US 8,630,377 B2). The efficient real time implementation makes this core an idel candidate to be used in cognitive radios. The spectrum sensing core is a fully parallel implementation which gives real time spectrum sensing capabilities allowing little to no interference to the incumbent. The spectrum sensing core is targeted to be used in radios developed based on IEEE802.22 standard.

This module is written in VHDL, capable of being used on any FPGA/ASIC architecture.


The following is the resource utilisation summary on a Kintex-7 410T part for data input bit width of 16, FFT size 128, power spectrum bit width of 18 and HMM window length of 5.

Slices Block RAMs Flip Flops
41763 15 41215

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