DVB-GSE Ethernet Tunnel IP Cores

High-throughput, low-latency Ethernet frame parsers & generators, and DVB-GSE encapsulator & de-encapsulator IP cores, for building datalink systems that transport Ethernet frames using DVB-GSE. The IP Core Worx DVB-GSE IP cores have been optimised for high performance, and also for DVB-S2/-T2/ C2 implementations that have strict resource/area constraints; for example, FPGA-based systems.

Pairing the IP Core Worx DVB-GSE Ethernet tunnel encapsulator core with its corresponding de-encapsulator core minimises the footprint & complexity of a bidirectional DVB-GSE system. (De-)Encapsulating of just layer 2 (Ethernet) traffic shifts the tasks of routing & QoS to external cores or devices (at each end of the Ethernet tunnel), increasing system flexibility and reducing FPGA resource requirements.

• Netlist or synthesisable RTL source code in VHDL
• Comprehensive verification test bench and vectors in VHDL
• User guides and documentation for integration & configuration
• Top-level entities for CCM-only, Ethernet-tunneling systems to aid with evaluation and rapid-prototyping

The following table shows the resource utilisation for various IP Core Worx DVB-GSE cores, when using Xilinx Vivado for synthesis, and targeting Xilinx ZYNQ devices. The designs satisfy the timing constraints at more than 160 MHz (ZYNC devices) – exceeding GbE performance with FPGA-based designs.