DVB-GSE de-encapsulator IP cores for IPv4/IPv6 network-layer traffic, and utilising a DVB-SPI-like interconnect for recieved BBFRAME’s, and AXI4-Stream interconnect for PDU output.
- GSE de-encapsulation and PDU re-assembly for IPv4/IPv6 packets
- Designed for high throughput and low latency
- Supports GSE packet header types for no labels, 6 byte labels, label reuse, and label-based filtering
- Parameterisable MTU’s and SRAM/buffer sizes
- Low (logic and SRAM) resource usage
- Support for both 16200b and 64800b BBFRAME’s, and all DATA FIELD sizes
- AXI4-Stream (8-bit) Interconnect
- Wishbone (SPEC B4) interface for control and packet/device statistics
- Includes BBFRAME parser, stream de-MUX, and de-scrambling cores
- Robust exception handling and with rapid recovery from
- Netlist or synthesisable RTL source code in VHDL
- Comprehensive verification test bench and vectors in VHDL
- User guides and documentation for integration & configuration
- Top-level entity for a CCM-only system, to aid with evaluation and rapid-prototyping
High-throughput, low-latency de-encapsulator IP cores for building DVB-GSE systems. The IP Core Worx DVB-GSE IP cores have been optimised for high performance, and also for DVB-S2/-T2/-C2 implementations that have strict resource/area constraints; for example, FPGA-based systems.
The following table shows the resource utilisation for various IP Core Worx DVB-GSE cores, when using Xilinx Vivado for synthesis, and targeting Xilinx ZYNQ devices. The designs satisfy the timing constraints at more than 160 MHz (ZYNC devices) – exceeding GbE performance with FPGA-based designs.